The present invention is generally directed to the processing of a microelectronic workpiece. More particularly, the present invention includes a method and apparatus for processing a microelectronic workpiece at an elevated temperature.
For purposes of the present application, a microelectronic workpiece is defined to include a workpiece formed from a substrate upon which microelectronic circuits or components, data storage elements or layers, and/or micro-mechanical elements are formed. Although the present invention is applicable to this wide range of products, the invention will be particularly described in connection with its use in the production of interconnect structures formed during the production of integrated circuits on a semiconductor wafer. Still further, although the invention is applicable for use in connection with a wide range of metal and metal alloys as well as in connection with a wide range of elevated temperature processes, the invention will be particularly described in connection with annealing of electroplated copper and copper alloys.
In the production of semiconductor integrated circuits and other microelectronic articles from microelectronic workpieces, such as semiconductor wafers, it is often necessary to provide multiple metal layers on a substrate to serve as interconnect metallization that electrically connects the various devices on the integrated circuit to one another. Traditionally, aluminum has been used for such interconnects, however, it is now recognized that copper metallization may be preferable. Copper interconnects can help alleviate many of the problems experienced in connection with the current aluminum technology.
The microelectronic fabrication industry has sought to use copper as the interconnect metallization by using a damascene and/or patterned plating electroplating process where holes, more commonly called vias, trenches and other recesses are used to produce the desired copper patterns. In the damascene process, the wafer is first provided with a metallic seed layer and barrier/adhesion layer that are disposed over a dielectric layer into which trenches are formed. The seed layer is used to conduct electrical current during a subsequent metal electroplating step. Preferably, the seed layer is a very thin layer of metal that can be applied using one of several processes. For example, the seed layer of metal can be laid down using physical vapor deposition or chemical vapor deposition processes to produce a layer on the order of 1000 angstroms thick. The seed layer can also be formed of copper, gold, nickel, palladium, and most or all other metals. The seed layer is formed over a surface that is convoluted by the presence of the trenches, or other device features, which are recessed into the dielectric substrate.
In single damascene processes using electroplating, a process employing two electroplating operations is generally employed. First, a copper layer is electroplated onto the seed layer in the form of a blanket layer. The blanket layer is plated to an extent which forms an overlying layer, with the goal of completely providing a copper layer that fills the trenches that are used to form the horizontal interconnect wiring in the dielectric layer. The first blanket layer is then subject, for example, to a chemical mechanical polish step in which the portions of the layer extending above the trenches are removed, leaving only the trenches filled with copper. A further dielectric layer is then provided to cover the wafer surface and recessed vias are formed in the further dielectric layer. The recessed vias are disposed to overlie certain of the filled trenches. A further seed layer is applied and a further electroplated copper blanket layer are provided that extend over the surface of the further dielectric layer and fills the vias. Again, copper extending above the level of the vias is removed using, for example, chemical mechanical polishing techniques. The vias thus provide a vertical connection between the original horizontal interconnect layer and a subsequently applied horizontal interconnect layer. Electrochemical deposition of copper films has thus become an important process step in the manufacturing of high-performance microelectronic products.
Alternatively, the trenches and vias may be etched in the dielectric at the same time in what is commonly called a “dual damascene” process. These features are then processed, as above, with barrier layer, seed layer and fill/blanket layer that fill the trenches and vias disposed at the bottoms of the trenches at the same time. The excess material is then polished, as above, to produce inlaid conductors.
The mechanical properties of the copper metallization can be quite important as the metal structures are formed. This is particularly true in connection with the impact of the mechanical properties of the copper metallization during chemical mechanical polishing. Wafer-to-wafer and within wafer grain size variability in the copper film can adversely affect the polish rate of the chemical mechanical processing as well as the ultimate uniformity of the surfaces of the polished copper structures. Large grain size and low variations in grain size in the copper film are very desirable.
The electrical properties of the copper metallization are also important to the performance of the associated microelectronic device. Such devices may fail if the copper metallization exhibits excessive electromigration that ultimately results in an open or short circuit condition in one or more of the metallization structures. One factor that has a very large influence on the electromigration resistance of sub-micron metal lines is the grain size of the deposited metal. This is because grain boundary migration occurs with a much lower activation energy than trans-granular migration.
To achieve the desired electrical characteristics for the copper metallization, the grain structure of each deposited blanket layer is altered through an annealing process. This annealing process is traditionally thought to require the performance of a separate processing step at which the semiconductor wafer is subject to an elevated temperature of about 400 degrees Celsius. The relatively few annealing apparatus that are presently available are generally stand-alone batch units that are often designed for batch processing of wafers disposed in wafer boats.
The present inventors have recognized substantial improvements over the foregoing processes and apparatus currently suitable for annealing of metal microstructures. To this end, they have developed an improved annealing apparatus that may be readily integrated into a processing tool incorporating a number of other processing reactors, including, for example, an electroplating reactor.